Dc voltage multiplier

ABSTRACT

A DC voltage multiplier having a plurality of voltage multiplying stages using transistors that are capacitively coupled to an inverter to conduct current in only one direction. A variable impedance is responsive to a signal to vary the factor of multiplication of the DC voltage multiplier between a maximum value and a lower value that is determined by the number of voltage multiplying stages affected by the variable impedance and bypassed within the multiplier by a unidirectional current conducting device.

United States Patent Beck et al.

[ Feb. 29, 1972 [54] DC VOLTAGE MULTIPLIER [72] Inventors: Charles ll.Beck, Chalfont; William F.

Meyers, Blue Bell, both of Pa.

M. Manon, Michlhi, i966, 5p; @7; @81" Electronics, Capacitors Add Up inVoltage Multiplier," H. R. Mallory, March 2, 1970, p. 104.

Primary Examiner-William M. Shoop, Jr. Attorney-Charles LUngemach andAlbin Medved [57] ABSTRACT A DC voltage multiplier having a plurality ofvoltage multiply- :tfiil ..321/l5 ins stages using transistors that arecapacitive), coupled to an [58] Field 321/15 inverter to conduct currentin only one direction. A variable impedance is responsive to a signal toy the factor of 5 References Cited tiplication of the DC voltagemultiplier between a maximum value and a lower value that is determinedby the number of UNITED STATES PATENTS voltage multiplying stagesaffected by the variable impedance 3,505,586 4/1970 Dulin ..321/15 andbypassed Within the multiplier by a unidirecfima' 3,513,376 5Il970 Hajek..321/15 conducting device- 3,529,23l 9 1970 B I 321/15 X 7Claims, 1Drawlngl igure OTHER PUBLICATIONS Electronics, C Converter Circuit UsesCapacitors, J,

[34 W INVERTER [38 59A. LOAD VARIABLE IMPEDANCE DC VOLTAGE MULTIPLIERBACKGROUND OF THE INVENTION The present invention is an improvement inDC voltage multiplier circuitry.

Commonly known prior art DC voltage multipliers employ a plurality ofrectifier-capacitor voltage multiplying stages to increase an inputvoltage to a higher level. These multipliers use semiconductor diodesfor the rectifiers. However, the power requirements of the diodes limitthe efficiency of such multipliers. Certain applications for voltagemultipliers require improved efficiency to allow the use of a verylow-voltage source to supply the necessary voltage level. The inventionis particularly useful in applications when, due to space and weightlimitations on the voltage source, a voltage multiplier is used toenable a small DC voltage source to deliver a higher voltage. It isadvantageous to have a voltage multiplier with improved efficiency toallow the use of as small a DC voltage source as is possible. Thepresent invention provides improved efficiency over prior art voltagemultipliers by reducing power losses and minimizing wasted sourceenergy.

It is also characteristic of the prior art DC voltage multipliers thatthe voltage output is not widely variable in response to a controlsignal. In many applications wherein a voltage multiplier is used, it isnecessary that the output of the voltage multiplier remain constant overa wide variation of input voltage. Since the DC voltage source isusually a small DC cell, the output voltage from the cell may varyduring the operative period. It is desirable to maintain the output ofthe voltage multiplier at a constant level for successful operation.This is achieved by using a voltage multiplier which can vary the factorof multiplication therein over a wide range in response to a controlsignal indicative of the variation in the output level of the DC source.

BRIEF SUMMARY OF THE INVENTION The present invention is an improved DCvoltage multiplier wherein each voltage multiplying stage consists of atransistor and a capacitor. Each transistor receives a low-levelalternating switching voltage via capacitive coupling to an inverterwhich cyclically inverts the polarity of the DC source across thevoltage multiplier input. Each transistor becomes conductive during onlyone-half of each cycle of the inverters output to conduct current inonly one direction. The result is that rectification if achieved by thetransistors without the high forward voltage drop characteristic ofsemiconductor diodes. The present invention achieves greater voltageefficiency as compared to prior art DC low input voltage multipliers.

A variable impedance that is connected in series with the voltagemultiplying stagesis responsive to a signal for varying its impedancewhich allows the voltage multiplier to vary the factor of multiplicationover a wide range. The factor of mu]: tiplication is greatest when theconductivity of the variable impedance is at a maximum. The factor ofvoltage multiplication is reduced by decreasing the conductivity of thevariable impedance until a lower limit is reached which is determined bythe number of voltage multiplying stages affected by said vari-v ableimpedance and bypassed by a unidirectional current conducting device.

It is an objective of the present invention to provide a low inputvoltage multiplier with increased efficiency.

It is a further objective of the present invention to provide a lowinput voltage multiplier that is responsive to a signal for varying thefactor of voltage multiplication over a wide range.

BRIEF DESCRIPTION OF THE DRAWING DESCRIPTION OF THE PREFERRED EMBODIMENTReferring to the drawing, the preferred embodiment'hasa.

pair of input terminals and 11 for connection to a DC source 12 havingthe polarity shown..A pair of output terminals 13 and 14 are providedfor connection to a load 15 which requires a DC signal.

An NPN-transistor 16 having an emitter 17, a base 18, and a collector 19is connected to input terminal 11 via emitter 17.

A second NPN-transistor 20 having an emitter 21, a base 22,

and a collector 23, is connected to collector 19 via emitter 21. A thirdNPN-transistor 24 having an emitter 25, a base 26, and a collector 27 isconnected to collector 23 via emitter 25. A fourth NPN-transistor 28having emitter 29, a base 30, and a collector 31 is connected to outputterminal14 via collector 31.

A variable impedance 32 having a control input 33 is connected betweencollector 27 and emitter 29. However, as will be explained in theoperation, variable impedance 32 may be located elsewhere in thecircuit.

An inverter 34 having a pair of input terminals 35 and 36 and a pair ofoutput terminals 37 and 38, is connected to input terminals 10 and 11via input terminals 35 and 36, respectively. Inverter output terminal 38is connectedto base 18 and emitter 21 via a capacitor 39 and a capacitor40 respectively, and also to base 26 and emitter 29 via a capacitor 41and a capacitor 42 respectively.

Inverter output terminals 37 is connected to base 22 and emitter 25 by acapacitor 43 and a capacitor 44, and alsoto base 30 and collector 31 viaa capacitor 45 and a capacitor 46 respectively. Inverter output terminal37 is further connected to output terminal 13.,

A resistor 47 is connected between base 18 and emitter 17, and aresistor 48 is connected between base 22 and emitter 21. Similarly, aresistor 49 is connected between base 26 and emitter 25, and a resistor50 is connected between base 30 and emitter 29.

A diode 51 has its anode connected'to emitter 29 and its cathodeconnected to input terminal 11.

OPERATION 5 The preferred embodiment of the present invention operatesto produce a theoretical maximum output voltage equal to approximatelyfour times the voltage it receives at inverter output terminals 37 and38; The actual multiplication is somewhat lower due to the-lossesoccurring in the circuit. Also, means are provided for varying outputfrom a maximum value to a lower value in response to a signal.

Inverter output terminals 37 and 38 are alternately connected to thepositive terminal of DC source 12 by inverter 34. When inverter outputterminal 38 becomes positive, transistors 16 and 24 become conductive,and transistors 20 and 28 are nonconductive. Variable impedance-32 isfully conductive when a maximum value of output is desired. The furthereffects of variable impedance 32 and diode 51 upon the operation will bediscussed later. With the conductivity of the transistors as stated,capacitors 40 and 42 become charged to a voltageapproximately equal tothe voltage of DC source 12.

When the polarity of inverter output terminals37 and 38 reverses makinginverter output I terminal; 37 positive, transistors 20 and 28 becomeconductive, and transistors 16 and 24 become nonconductive due to thecharge on capacitors 39 and 41 decaying through resistors 47 and 49respectively. Therefore, the charge on capacitors 40 and 42 cannotescape. through transistors 16 and 24. Now, capacitors 44 and 46approach a voltage equal to approximately twice the voltage of DC source12 since capacitor 44 is connected in series with DC source 12 andcapacitor 40 and capacitor 46 is connected in series with DC source 12and capacitor 42.

Again, the polarity of inverter output terminals 37 and 38 is reversedby inverter 34 tomake inverter output terminal 38 positive. Transistors16 and 24 again become conductive, and transistors 20 and 28 become,nonconductive due to the chargeonrcapacitors .43 and 45 decaying throughresistors 48 and 50, respectively. Capacitor 40 is again charged to avoltage approximately equal to the voltage of DC source 12, but

capacitor 42 becomes charged to a voltage approaching three times thevoltage of DC source 12, because it is connected in series with DCsource 12 and capacitor 44 which was previously charged to approximatelytwice the voltage of DC source 12.

When inverter 34 again reverses the polarity of the input voltage tomake inverter output terminal 37 positive, transistors 20 and 28 becomeconductive and transistors 16 and 24 become nonconductive. Capacitor 46eventually becomes charged to a voltage of approximately four times thevoltage of DC source 12 since capacitor 46 is connected in series withDC source 12 and capacitor 42 which was previously charged to a voltageof approximately three times the voltage of DC source 12. This operationis continuous to maintain a voltage of approximately four times thevoltage of DC source 12 at output terminals 13 and 14.

The above description relates to the operation of the present inventionwhen it produces a maximum value of output voltage. However, as theconductivity of variable impedance 32 is reduced, the voltage output isreduced since capacitors 42 and 46 charge less fully than when a maximumvalue of output is produced. Variable impedance 32 could be anyapparatus, such as a transistor or a rheostat, which is responsive tosome signal to vary its impedance. When variable impedance 32 becomessufficiently nonconductive, capacitors 42 and 46 receive very littlecharge from capacitors 40 and 44 due to the reduced charging currentflowing therefrom. Then, capacitors 42 and 46 become charged via diode51 and inverter 34 by DC source 12. Diode 51 prevents the charge oncapacitor 42 from escaping except through transistor 28 to capacitor 46.Since capacitor 42 is charged to the voltage of DC source 12, capacitor46 is charged to twice the voltage of DC source 12 when transistor 28becomes conductive. Therefore, a lower limit for the output voltage ofthe preferred embodiment of the present invention is approximately twicethe voltage of the DC input voltage due to the operation of diode 51.

Of course, the number of voltage multiplying stages may be increased ordecreased without altering the spirit or scope of the present invention.Also, variable impedance 32 and the anode of diode 51 may be placedanywhere in the circuit such that as variable impedance 32 becomesnonconductive, a plurality of the voltage multiplying stages areeffectively removed from the circuit, and the remaining stages areallowed to continue operation by means of diode 51, thereby reducing theoutput of the circuit to a lower value. Transistors 16, 20, or 24 mayalso be utilized as the variable impedance by regulating the decay ofcharge from 47, 48, or 49 rather than permitting it to pass directly to17, 21, or 25 respectively.

A number of bypassing networks comprising variable impedance-diodecombinations can be employed to provide an option, whereby throughoperation of one or more of such bypassing networks a different numberof voltage multiplying stages can be removed from the circuit. Diode 51may also be a transistor for reduction of voltage loss.

The output of the multiplier may also be placed in series with the DCpower source to provide additional voltage as in boost circuits.Dissipation of energy may be minimized by reducing the inverterfrequency or pulse width for vernier variations in output voltage andremoving one or more multiplying stages at a time for major ratiovariations.

The embodiment disclosed in the preceding specification is preferred.The present invention is designed for low power operation which isrequired with a low power DC source. However, variations in thearrangement and construction of the circuit disclosed by the precedingspecification such as the use of PNP-transistors may be apparent to oneof ordinary skill in the art which do not depart from the nature andprinciple of the present invention.

We claim as our invention:

l. A DC voltage multiplier for raising the voltage level of a DC voltagesource by a factor of multiplication comprising:

input means for connection to said DC source; first and second outputterminals;

a plurality of transistors, each of said transistors having a controlelectrode and further having first and second current carryingelectrodes, each of said transistors being responsive to a signal atsaid control electrode for conducting a unidirectional current from saidfirst current carrying electrode to said second current carryingelectrode, said transistors being connected in series between saidsecond output terminal and said DC source for conducting aunidirectional current therebetween;

an inverter having a first inverter output tenninal and a secondinverter output terminal, said inverter being connected to said DCsource for causing the polarity of said DC source to cyclically reversebetween said first and second inverter output terminals;

capacitive coupling means connecting said first inverter output terminaltosaid control electrodes of alternate of said transistors and furtherconnecting said second inverter output terminal to said controlelectrodes of the remaining of said transistors;

means connecting said first inverter output terminal to said firstoutput terminal;

capacitive storage means connecting said first current carryingelectrodes of said alternate of said transistors to said first inverteroutput terminal and further connecting said first current carryingelectrodes of said remaining of said transistors to said second inverteroutput terminal;

impedance means connected between said control electrode and said secondcurrent carrying electrode of each of said plurality of transistors;

a variable impedance connected in series with said current carryingelectrodes of said transistors, said variable impedance beingcontrollable for varying the factor of multiplication from a maximumvalue; and

unidirectional current conducting means connected in parallel with saidvariable impedance and a predetermined number of said transistors forestablishing a lower limit on the variation of the factor ofmultiplication.

2. The DC voltage regulator of claim 1 wherein said unidirectionalcurrent conducting means comprises a diode.

3. The DC voltage regulator of claim 2 wherein said variable impedancecomprises a transistor.

4. A DC voltage multiplier circuit including a DC-to-AC inverter and aplurality of multiplier stages of rectifier-capacitor combinations,wherein the factor of voltage multiplication is determined by the numberof said multiplier stages actively engaged in the circuit, animprovement comprising:

a bypassing network including a variable impedance connected in serieswith said multiplier stages and a unidirectional current conductingmeans connected in parallel with said variable impedance and at leastone of said multiplier stages, said bypassing network effecting variableengagement of said multiplier stage through the control of said variableimpedance, thereby allowing electronic control of the voltagemultiplication of said circuit over a wide range from a maximum value toa lower value. a

5. Apparatus according to claim 4 wherein said unidirectional currentconducting means is connected in parallel with said variable impedanceand a plurality of said multiplier stages.

6. Apparatus according to claim 4 wherein a plurality of bypassingnetworks are provided, each of said bypassing networks effectingvariable engagement of at least one of said multiplier stages.

7. Apparatus according to claim 4 wherein said rectifiercapacitorcombinations comprise transistor-capacitor combinations.

1. A DC voltage multiplier for raising the voltage level of a DC voltage source by a factor of multiplication comprising: input means for connection to said DC source; first and second output terminals; a plurality of transistors, each of said transistors having a control electrode and further having first and second current carrying electrodes, each of said transistors being responsive to a signal at said control electrode for conducting a unidirectional current from said first current carrying electrode to said second current carrying electrode, said transistors being connected in series between said second output terminal and said DC source for conducting a unidirectional current therebetween; an inverter having a first inverter output terminal and a second inverter output terminal, said inverter being connected to said DC source for causing the polarity of said DC source to cyclically reverse between said first and second inverter output terminals; capacitive coupling means connecting said first inverter output terminal to said control electrodes of alternate of said transistors and further connecting said second inverter output terminal to said control electrodes of the remaining of said transistors; means connecting said first inverter output terminal to said first output terminal; capacitive storage means connecting said first current carrying electrodes of said alternate of said transistors to said first inverter output terminal and further connecting said first current carrying electrodes of said remaining of said transistors to said second inverter output terminal; impedance means connected between said control electrode and said second current carrying electrode of each of said plurality of transistors; a variable impedance connected in series with said current carrying electrodes of said transistors, said variable impedance being controllable for varying the factor of multiplication from a maximum value; and unidirectional current conducting means connected in parallel with said variable impedance and a predetermined number of said transistors for establishing a lower limit on the variation of the factor of multiplication.
 2. The DC voltage regulator of claim 1 wherein said unidirectional current conducting means comprises a diode.
 3. The DC voltage regulator of claim 2 wherein said variable impedance comprises a transistor.
 4. A DC voltage multiplier circuit including a DC-to-AC inverter and a plurality of multiplier stages of rectifier-capacitor combinations, wherein the factor of voltage multiplication is determined by the number of said multiplier stages actively engaged in the circuit, an improvement comprising: a bypassing network including a variable impedance connected in series with said multiplier stages and a uNidirectional current conducting means connected in parallel with said variable impedance and at least one of said multiplier stages, said bypassing network effecting variable engagement of said multiplier stage through the control of said variable impedance, thereby allowing electronic control of the voltage multiplication of said circuit over a wide range from a maximum value to a lower value.
 5. Apparatus according to claim 4 wherein said unidirectional current conducting means is connected in parallel with said variable impedance and a plurality of said multiplier stages.
 6. Apparatus according to claim 4 wherein a plurality of bypassing networks are provided, each of said bypassing networks effecting variable engagement of at least one of said multiplier stages.
 7. Apparatus according to claim 4 wherein said rectifier-capacitor combinations comprise transistor-capacitor combinations. 